TY  - BOOK
AU  - Jayanthy,S.
AU  - Bhuvaneswari,M.C.
TI  - Test generation of crosstalk delay faults in VLSI circuits
SN  - 9789811324925
U1  - 621.3815 
PY  - 2019///
CY  - Singapore
PB  - Springer
KW  - Microprogramming
KW  - Logic design
KW  - Circuits and system
N1  - Includes bibliographical references
N2  - This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing
ER  -