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Test generation of crosstalk delay faults in VLSI circuits / (Record no. 140379)

MARC details
000 -LEADER
fixed length control field 01369nam a22002417a 4500
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20260408155351.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 260407s2019 |||||||| |||| 00| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9789811324925
040 ## - CATALOGING SOURCE
Transcribing agency PK-LaUMT
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Item number JAY-T
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Jayanthy, S.
245 10 - TITLE STATEMENT
Title Test generation of crosstalk delay faults in VLSI circuits /
Statement of responsibility, etc by S. Jayanthy and M. C. Bhuvaneswari
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc Singapore :
Name of publisher, distributor, etc Springer,
Date of publication, distribution, etc 2019
300 ## - PHYSICAL DESCRIPTION
Extent xi, 156 p.
500 ## - GENERAL NOTE
General note Includes bibliographical references
520 ## - SUMMARY, ETC.
Summary, etc This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing
546 ## - LANGUAGE NOTE
Language note Eng
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Microprogramming
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic design
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Circuits and system
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Bhuvaneswari, M. C.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Books
Holdings
Withdrawn status Lost status Damaged status Home library Current library Date acquired Full call number Barcode Date last seen Price effective from Koha item type
      UMT Main Campus UMT Main Campus 2026-04-07 621.35815 JAY-T 152301 2026-04-07 2026-04-07 Books